The field of the invention relates generally to the fabrication of semiconductor-on-insulator composite substrates, such as silicon-on-sapphire (SOS), and more particularly to a method and structure for fabricating transistors in integrated circuits provided in silicon-on-sapphire or other silicon-on-insulator material.
Local oxide isolation of silicon, referred to as LOCal Oxidation of Silicon (LOCOS), is the isolation technique most commonly used in present silicon-on-insulator (SOI) technology. The objective of LOCOS isolation and other conventional isolation techniques is to isolate transistors of opposite polarity from each other using a combination of ion implantation and thermal oxidation techniques. A LOCOS process is typically used for isolating complimentary metal oxide silicon (CMOS) transistors in SOI technology. However, as a result of isolating the active silicon islands containing transistors from one another with conventional LOCOS isolation methods, the implanted ions (typically boron) may diffuse beyond the edge or corner of the transistor, where such excess ions undesirably degrade transistor performance.
Intrinsic stresses at the edge of a nitride film give rise to horizontal forces that act on the substrate. Under some circumstances, such stress can exceed the critical stress for dislocation generation in silicon, and thus become a source of fabrication-induced defects. A pad oxide layer is used to combat stress and to avoid dislocation generation. The pad oxide layer reduces forces transmitted to the silicon at the nitride edge.
An example of the process for conventional LOCOS isolation techniques in SOI technology is shown in FIGS. 4A-4C. Active regions are defined with standard photolithography. A resist pattern is normally used to protect all of the areas of the silicon where active devices will be formed. The nitride layer is then dry etched, and the pad oxide is etched by means of either a dry or wet chemical process. After the pad oxide has been etched, the resist is not removed, but rather is left in place to serve as a masking layer during a channel stop implant step. An additional mask is required for blocking, for example, a boron implant over regions that do not require boron as shown in FIG. 4B.
An implant is next performed in the selected field regions to create a channel stop doping layer under the field oxide. In N-channel MOS (NMOS) transistors, a P.sup.+ implant of boron is used. In P-channel MOS transistors (PMOS), an N.sup.+ implant of arsenic or phosphorous is utilized. After the channel stop implant has been completed, the masking resist is stripped away.
The movement of boron into the active N-channel region after implantation and oxidation is referred to as the .DELTA.W characteristic. Increases in boron dosage requirements result in larger .DELTA.W characteristics, indicating substantial lateral boron diffusion. In order for a transistor to function with a large .DELTA.W, it must be designed with significantly greater area to compensate for the increased amount of boron present within the transistor. Increasing the size of a transistor has the disadvantage of ultimately decreasing operating speed and increasing the cost per chip. Further, very large scale integration (VLSI) technology is not feasible with large transistors.
Another disadvantage of the conventional method of isolating active silicon islands is that the thickness of the silicon layer determines the time and temperature necessary to grow the oxide layer. However, such time and temperature characteristics may not be the same time and temperature parameters required to mobilize the implanted boron through the MOSFET, and into the edges. Consequently, the two separate sets of time and temperature characteristics affect one another. It is always desirable in wafer processing that each processing step be independent of the next step, in order to be able to change one processing step without affecting another.
Therefore, what is needed are improved process conditions in order to control edge transistor leakage, and in order to enhance a transistor's performance. It would be a significant advantage over current SOI LOCOS isolation processes if less lateral boron diffusion occurred in the edges of a transistor during processing, thereby resulting in smaller boron dose requirements. With a decrease in boron dosage, the .DELTA.W would shrink, ultimately producing better transistor operating characteristics. Additionally, transistor size advantageously could be reduced.
It would be a significant advantage over typical SOI technology to implement an isolation process that would not only control, but substantially prevent edge transistor leakage. That is, it would be a significant advantage over conventional SOI LOCOS processes to substantially prevent lateral boron diffusion into a transistor. This advantageously would enable a process to use smaller boron doses and still obtain desired transistor performance.
Therefore, what is needed is an improved isolation process with minimum boron dose requirements to reduce or eliminate lateral diffusion. Decreasing boron dosages would reduce the .DELTA.W, ultimately producing better transistor characteristics, including reducing transistor size. Such an improved isolation process should reduce fabrication process time and simplify manufacturing, thereby resulting in higher yields.